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发布于 2026-09-26 英文原文

首席封装设计工程师

Principal Package Design Engineer

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点美国加利福尼亚州圣何塞 / 德克萨斯州奥斯汀(混合办公) 薪资面议

职位概要

该职位为Renesas Electronics America半导体功率产品组招聘首席封装设计工程师,工作地点为圣何塞或奥斯汀,采用混合办公模式。主要职责包括:主导先进半导体封装方案的设计、开发与认证,涵盖倒装芯片、晶圆级封装(WLP/FOWLP)、面板级封装、2.5D/3D封装、系统级封装(SiP)、BGA/CSP及晶圆对晶圆/芯片对晶圆异构键合等;根据电气、热、机械、可靠性和成本需求定义封装架构并进行仿真分析;推动OSAT与供应商选型及新产品导入;与IC设计、产品定义、基板、板级、热、可靠性、应用及制造团队跨职能协作;负责封装布局评审、叠层定义、材料选择与互连策略;开展信号完整性/电源完整性、热性能、机械应力/翘曲及可制造性设计(DFM)仿真;制定组装流程与工艺要求,主导封装认证、DOE规划、失效分析与可靠性测试;解决新产品导入、认证及量产爬坡中的封装问题,并与供应商合作提升良率。任职要求:电气工程、材料科学、机械工程、化学工程等相关专业硕士或博士学历,5年以上先进半导体封装或先进电子封装与系统集成经验;深入掌握先进封装技术、材料、组装工艺及应用系统集成,熟悉AI基础设施与数据中心电源管理;具备热、机械、电气交互分析及CAD/仿真工具实操经验;熟悉封装可靠性测试与认证标准;有OSAT、基板供应商及半导体供应链合作经验;具备封装失效排查、根因分析与纠正措施能力及项目领导力。优先条件包括:功率半导体器件(Si/SiC/GaN MOSFET、功率模块、智能功率模块)封装经验,高性能计算/AI/ML硬件或移动产品经验,熟悉Cadence Allegro、SolidWorks、ANSYS、COMSOL、JMP/Minitab等工具,了解JEDEC/IPC标准,具备W2W、D2W、D2D 3D异构集成及芯粒封装经验。该职位可能需偶尔出差至供应商、OSAT或研发/制造基地。

职位描述

Job Description Principal Package Design Engineer Location: Hybrid at main Renesas Electronics America locations (San Jose, CA / Austin, TX) Department: Semiconductor Power Product Group Reports To: Senior Principal, Device Design Packaging Technology, Strategy, Operations Position Summary We are seeking a Principal Package Design Engineer to lead the development and integration of next-generation packaging solutions for high-performance semiconductors and electronic products. This role will focus on advanced package architecture, assembly processes, thermal and mechanical reliability, and cross-functional collaboration with design, applications, product engineering, manufacturing, suppliers, and quality teams. The ideal candidate has deep expertise in semiconductor packaging technologies and a strong track record of bringing complex products from concept through qualification and high-volume production. Key Responsibilities Lead Advanced Packaging Initiatives: Lead the design, development, and qualification of advanced semiconductor packaging solutions, including: Flip-chip, Chip Embedding Wafer-level packaging (WLP/FOWLP) Panel-level packaging (laminate, molding) 2.5D/3D packaging System-in-package (SiP) Ball grid array (BGA/CSP) Wafer-to-wafer and die-to-wafer heterogeneous bonding Architecture & Simulation: Define package architecture based on electrical, thermal, mechanical, reliability, and cost requirements with hands-on, deep simulation expertise. OSAT & Vendor Strategy: Drive package technology and OSAT selection and development for new product introductions (NPI). Cross-Functional Collaboration: Work closely with IC design, product definers, substrate, board, thermal, reliability, applications, and manufacturing teams to ensure package compatibility and performance. Layout & Stack-Up: Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy. Simulations & Modeling: Perform and guide others on simulations and analysis related to: Signal integrity / power integrity Thermal performance Mechanical stress / warpage Design for manufacturability (DFM) Assembly & Qualification: Develop assembly flows and process requirements for OSATs and manufacturing partners. Lead package qualification activities, including DOE planning, failure analysis, and reliability testing. Yield & Issue Resolution: Resolve packaging-related issues and challenges during NPI prototype builds, qualification, and production ramp. Collaborate with suppliers and internal/external manufacturing partners on process improvements, material evaluation, and yield optimization. Documentation & Leadership: Create and maintain package specifications, design rules, process documentation, and technical reports. Mentor junior engineers and provide technical leadership across packaging initiatives. Qualifications Required Qualifications Education: MSc or PhD degree in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field. Experience: 5+ years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration. Technical Depth: Strong hands-on knowledge of advanced packaging technologies, materials, assembly processes, and application system integration as they apply to AI infrastructure and data center power management. Reliability & Tools: Deep understanding of thermal, mechanical, and electrical interactions in package design and extensive, hands-on model setup, simulations, and analysis. Strong background in CAD and simulation tools. Experience with package reliability testing and qualification standards. Supply Chain: Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains. Problem Solving & Leadership: Proven ability to troubleshoot packaging failures, drive root cause/corrective action, and demonstrate strong project leadership and cross-functional communication skills. Preferred Qualifications Master’s or PhD in a relevant engineering discipline. Experience with power semiconductor devices and packaging including Si/SiC/GaN MOSFETs, Power Modules, Intelligent Power Modules, and their applications in consumer, industrial, automotive, and high-performance computing markets. Experience with power products in high-performance computing, AI/ML hardware, or mobile products. Hands-on experience with tools for package design and simulation such as: Cadence Allegro Package Designer SolidWorks ANSYS COMSOL JMP / Minitab Knowledge of JEDEC standards, IPC standards, and semiconductor qualification methods. Experience in W2W, D2W, D2D 3D heterogeneous integration and chiplet-based packaging. Key Skills Advanced package concept engineering and design Materials selection and development Thermal and mechanical simulations and analysis Failure analysis & reliability engineering Design for Manufacturability (DFM/DFX) Process development & supplier collaboration Technical leadership & problem-solving Success in This Role A successful Principal Package Design Engineer will: Deliver robust package solutions that meet performance, reliability, and cost targets. Enable smooth product transfer from concept to development to manufacturing. Reduce packaging risks through strong technical analysis, hands-on simulations, and qualification planning. Improve yield, quality, and manufacturability through collaboration with internal and external partners. Working Conditions May require occasional travel to supplier, OSAT, or design/manufacturing/R&D sites. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.