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发布于 2026-10-21 英文原文

首席验证工程师

Senior Principal Design Verification Engineer

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点Chandler, AZ, us 薪资面议

职位概要

Renesas正在招聘一名经验丰富的首席验证工程师,负责领导汽车PMIC(电源管理集成电路)产品线的验证工作。该职位需要具备混合信号验证方法的深厚专业知识,以及指导初级工程师、推动多产品平台验证策略的领导能力。理想候选人应全面了解模拟、数字和混合信号验证技术,并具备调试复杂汽车电源管理系统的实操经验。主要职责包括:设计和构建混合信号验证环境,包括PMIC设计的实数模型(RNM)和AMS模型集成;制定并实施汽车PMIC产品的全面验证计划和策略,确保符合ISO 26262、AEC-Q200等汽车安全标准;搭建并优化门级仿真(GLS)流程,与RTL仿真结果关联以识别和解决差异;领导开关模式稳压器、LDO稳压器和混合信号接口等复杂模拟模块的调试活动;进行深入的RTL和门级仿真,分析PVT角下的时序、功耗和功能正确性;与设计、应用工程、ATE和硅验证等跨职能团队紧密合作;指导和带领初级验证工程师,定义最佳实践并建立验证方法;推动验证工具、方法和基础设施的持续改进,评估新兴验证技术和基于AI的解决方案;创建和维护验证文档、测试计划和覆盖率。任职资格:电气工程、计算机工程或相关专业硕士或博士;12年以上混合信号或模拟电路验证经验;深入理解混合信号验证环境架构和实现;具备RNM和AMS模型集成实操经验;熟练使用RTL和行为仿真工具(如Spectre、Xcelium);深入理解GLS流程并能搭建和调试GLS仿真;具备调试模拟模块(开关模式稳压器、LDO、带隙、基准电路)和数字RTL的丰富经验;具有汽车PMIC或电源管理IC设计与验证经验;熟练使用Verilog、SystemVerilog和/或基于SPICE的语言;扎实理解UVM、断言、覆盖率驱动验证等方法;具有功能、硅后、ATE测试关联等多验证领域接口经验;优秀的解决问题和调试能力,具备较强的分析思维;具有领导和指导经验。Renesas是嵌入式半导体解决方案提供商,全球拥有超过21,000名工程师,业务遍及30多个国家,致力于汽车、工业、基础设施和IoT领域的世界领先技术。公司文化TAGIE强调透明、敏捷、全球、创新和创业精神,提供有竞争力的薪酬福利。Renesas是平等机会和平权行动雇主,重视多样性。

职位描述

Job Description Position Overview Renesas is seeking an experienced Principal Verification Engineer to lead the verification efforts for our Automotive PMIC (Power Management Integrated Circuit) product line. This role combines deep expertise in mixed-signal verification methodology with strong leadership capabilities to mentor junior engineers and drive verification strategy across multiple product platforms. The ideal candidate will have comprehensive knowledge of analog, digital, and mixed-signal verification techniques, combined with hands-on experience debugging complex automotive power management systems. Key Responsibilities • Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration for PMIC designs • Develop and implement comprehensive verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200) • Set up and optimize Gate-Level Simulation (GLS) flows, correlating with RTL simulation results to identify and resolve discrepancies • Lead debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces • Conduct in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners • Collaborate closely with cross-functional teams: Design, Application Engineering, ATE (Automatic Test Equipment), and Silicon Validation to ensure seamless verification handoffs • Mentor and lead junior verification engineers, defining best practices and establishing verification methodologies • Troubleshoot and debug complex design issues involving interactions between analog and digital domains using simulation and measurement techniques • Drive continuous improvement of verification tools, methodologies, and infrastructure, evaluating emerging verification technologies and AI-based solutions • Create and maintain comprehensive verification documentation, test plans, and coverage Qualifications • MS or PhD in Electrical Engineering, Computer Engineering, or related • 12+ years of experience in mixed-signal or analog circuit verification • Deep understanding of all aspects of mixed-signal verification environment architecture and implementation • Hands-on experience with Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration • Proficiency in RTL and behavioral simulation tools (e.g., Spectre, Xcelium) • Strong understanding of Gate-Level Simulation (GLS) flows and ability to set up and debug GLS simulations • Proven expertise debugging both analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL • Experience with automotive PMIC or power management IC design and verification • Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages • Solid understanding of verification methodologies: UVM, assertions, coverage-driven verification • Experience interfacing with multiple verification domains: functional, post-silicon, ATE test correlation • Excellent problem-solving and debugging skills with strong analytical mindset • Leadership and mentoring experienc Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.