发布于 2026-10-06
英文原文
后端物理设计工程师
Sr. Staff Engineer - Physical Design
ルネサス エレクトロニクス
| 职种 | 工程 | 雇用形态 | — |
|---|---|---|---|
| 工作地点 | Bengaluru, KA, in | 薪资 | 面议 |
职位概要
Renesas(瑞萨电子)是全球领先的半导体公司之一,致力于打造更安全、更健康、更环保、更智能的世界,在汽车、工业、基础设施和物联网市场提供产品解决方案。现招聘一名经验丰富、技术能力强的后端物理设计工程师,负责下一代高性能SoC的物理实现。主要职责包括:负责从RTL到GDSII的完整物理设计流程,涵盖布局规划、综合、布局、时钟树综合(CTS)和布线;优化功耗、性能和面积(PPA),采用多电压域、电源门控(UPF)和数据通路优化等先进技术;推动多工艺角和多工作模式下的静态时序分析(STA),解决建立/保持违例、信号完整性和跨时钟域约束问题;执行DRC、LVS、EMIR分析和等价性检查(LEC/Formality);与RTL前端、DFT和签核团队紧密协作;使用Tcl、Python或Perl进行脚本自动化。任职要求:约10年以上物理设计实现经验;电气工程、计算机工程或相关专业学士或硕士学位;深入理解EDA工具(Fusion Compiler、Innovus、Primetime、Tempus、VCLP、LEC、Calibre、Red Hawk);具备STA、功耗分析和信号完整性分析能力;优秀的问题解决能力和团队协作沟通能力;有指导初级工程师经验者优先。Renesas拥有约21000名员工,遍布30多个国家,秉持透明、敏捷、全球化、创新和创业精神的企业文化,重视多元化与包容性,提供具有竞争力的薪酬福利。
职位描述
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking an experienced and highly technical Backend Physical Design Engineer to drive the physical implementation of our next-generation, high-performance SoCs. You will own the complete RTL-to-GDSII flow, focusing heavily on power recovery, clock tree optimization, and pushing aggressive PPA metrics on advanced technology nodes Key Responsibilities RTL-to-GDSII Execution: Own and drive the end-to-end physical design implementation, including floor planning, synthesis, placement, Clock Tree Synthesis (CTS), and routing. PPA Optimization: Fine-tune the design to meet stringent Power, Performance, and Area (PPA) targets. Employ advanced techniques like multi-voltage domains, power gating (UPF), and datapath optimization to minimize power while maximizing speed. Timing Closure & STA: Drive Static Timing Analysis (STA) across multiple corners and operating modes. Resolve setup/hold violations, signal integrity issues, and clock domain crossing constraints. Physical & Formal Verification: Execute Design Rule Checks (DRC), Layout Versus Schematic (LVS), electromigration/IR drop (EMIR) analysis, and Equivalence Checking (LEC/Formality) to ensure design reliability and manufacturability. Cross-Functional Collaboration: Work closely with RTL (Frontend), DFT, and Signoff teams to iterate on designs and structural changes for optimal PPA. Programming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies Qualifications Experience of about 10+ years in Physical design implementation Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Ability to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle. Extensive experience in physical design PPA activities, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk. Strong understanding of static timing analysis, power analysis, and signal integrity analysis. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment and communicate clearly with cross-functional teams. Experience in mentoring and coaching junior engineers is a plus. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .