发布于 2026-10-22
英文原文
高级数字设计工程师
Senior Digital Engineer
ルネサス エレクトロニクス
| 职种 | 工程 | 雇用形态 | — |
|---|---|---|---|
| 工作地点 | 美国亚利桑那州钱德勒 | 薪资 | 面议 |
职位概要
瑞萨电子正在为其位于美国亚利桑那州钱德勒的硬件开发团队招聘一名高级数字设计工程师。该职位负责为复杂的混合信号应用设计功耗和面积优化的数字电路,包括解读高层需求,在先进工艺节点下为混合信号数据转换和电源管理产品架构、设计并集成低功耗数字电路。需支持从概念到量产的全产品生命周期,与模拟和验证工程师紧密合作,交付高质量硅解决方案。职责包括设计满足时序、面积、功耗及标准规范的RTL,顶层集成与模块/顶层仿真,参与混合信号设计全流程(微架构、设计划分、Verilog/SystemVerilog RTL设计、时序约束生成、综合、与P&R团队交互、时序分析、LINT、CDC、RDC、UPF),支持DFT策略与实现,协助顶层测试平台调试及RTL与门级仿真,开发行为模型与设计文档,参与设计评审,进行硅评估并记录勘误。要求5年以上无线手持、数据转换或电源管理领域数字设计经验,电气/电子/计算机工程或相关学位,精通Verilog/SystemVerilog RTL,熟悉ASIC设计方法学、Lint/CDC/RDC工具、模块与芯片级验证技术,具备RTL与门级仿真调试能力,英语书面与口语流利,能短期出差,独立且协作工作。优先考虑混合信号设计、设计约束与P&R交接、STA与时序收敛、低功耗设计(时钟与电源门控UPF)、功耗分析与优化、UVM验证方法学、AMBA或I2C等协议经验。瑞萨提供有竞争力的薪酬与福利,倡导TAGIE文化(透明、敏捷、全球、创新、创业),是平等机会雇主。
职位描述
Job Description Renesas Electronics is seeking a skilled and motivated Senior Digital Design Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications. Interpret high level requirements to architect, design & integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes. Support full product lifecycle from concept to mass-production; communicating closely with wider organization through the various stages of silicon development. Work closely with Analog and Verification engineers to deliver high-quality silicon solutions. Ensuring digital development process is state-of-art and achieves budget, schedule, and project deliverable goals. Designing digital RTL that meets timing, area, power and any adhering standards specifications. Integrating design at the top level and running block & top-level simulations. Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / SystemVerilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF. Working closely with P&R team to generate a layout that meets timing, area, and power requirements. Support DFT strategy and implementation, and review test case development. Assisting with top level test-bench debug, and running RTL & gate level simulations Working with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification. Supporting analog team to develop AMS, SystemVerilog or Verilog-real behavioral models. Developing detailed block & chip level design documents and collateral. Holding and participating in key design reviews and completion of various checklists. Perform silicon evaluation as required. Document device errata, develop work-around solutions, implement engineering changes when necessary. Qualifications >5 years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management. Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline. Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design. Strong understanding of ASIC design methodology. Strong understanding of Lint, CDC & RDC tools. Strong understanding of block-level & chip-level verification techniques. Strong & proven ability to debug both RTL & gate-level simulations. Mandatory competence in written and verbal English. Willingness to travel domestically or internationally on short notice. Ability to work independently and collaboratively. Preferred: experience with mixed-signal design methodologies. Preferred: experience developing design constraints and hand-off to P&R. Preferred: experience with STA and timing closure. Preferred: experience with low-power design techniques, including clock and power gating (UPF). Preferred: experience with power analysis and optimization. Preferred: experience with advanced verification methodologies (UVM). Preferred: experience with industry-standard protocols such as AMBA or I2C. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.