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发布于 2026-10-16 英文原文

下一代高端MPU系统级与全芯片架构师

Principal SoC System Architect

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点Raanana, il 薪资面议

职位概要

该职位负责下一代高端MPU产品的系统级与全芯片架构,面向机器人、物理AI、工业网络与控制、高级视觉、多模态AI处理等高性能嵌入式应用。需定义可扩展、可复用的SoC架构,将异构计算、摄像头/视觉、AI、HMI/显示、内存与互连、连接性、安全、功能安全及平台管理能力集成为软硬件协同的产品,覆盖多个市场与性能层级。将产品战略、客户用例、代表性工作负载和技术能力转化为架构决策,在性能、功耗、散热、面积、成本、可扩展性、软件兼容性、实现可行性、风险与上市时间之间取得平衡。需与全球跨职能团队(产品、业务、架构、硬件、软件/固件、验证、实现及客户团队)协作,并与产品线和工程负责人(总监至副总裁级)沟通架构方案、权衡取舍并推动决策落地。主要职责包括:主导从早期产品定义到硅片点亮和产品验证的全芯片架构;制定架构提案并对齐技术与业务相关方;定义全芯片组成、系统数据与控制流、共享资源、子系统接口与集成架构;分配性能、功耗、散热、内存、带宽、延迟、QoS、面积与成本预算;定义代表性并发工作负载并用定量分析识别瓶颈、验证架构选择;通过早期相关方参与和明确系统划分、接口、需求、假设与约束推动软硬件协同开发;评估性能、功耗、面积、成本、软件影响、实现风险、进度与技术约束之间的权衡。任职要求:具备高度集成MPU或应用处理器级SoC顶层架构的丰富经验,并有从产品与用例定义到实现、硅片点亮和产品验证的完整主导经历;广泛了解异构计算、内存层次、缓存一致性、互连、共享资源、高速I/O、系统控制、电源管理、安全、软件可见架构与平台集成;能将客户用例与并发工作负载转化为系统数据与控制流、需求、KPI、资源预算与架构决策;具备定量建模分析系统性能、识别瓶颈并调整架构或系统配置的能力;能将软件与固件需求、执行约束及生态因素纳入软硬件划分、接口与SoC架构决策;具备评估全芯片可行性并推动性能、功耗、散热、面积、成本、实现风险与进度权衡的经验;具备较强的技术领导力与沟通能力,能在全球团队和高级相关方之间构建不完整需求、制定严谨提案并推动对齐。优先条件:具备支持机器人、物理AI、工业网络与控制、高级视觉、多模态AI等复杂工作负载的高性能MPU或应用处理器SoC经验;在计算、内存与互连、一致性、系统性能、实时处理、功耗与散热架构、安全或全芯片集成等主要SoC架构领域有深厚专长;具备跨产品系列或性能与成本层级定义可扩展、可复用SoC架构的经验;具备功能安全或混合关键性SoC架构经验,包括隔离、故障遏制、诊断及相关ISO 26262或IEC 61508考量。学历要求:电气工程、计算机工程、计算机科学或相关技术领域学士或硕士学位;优先考虑高级学位、相关专利、出版物、标准参与或在SoC/系统架构方面公认的技术领导力。Renesas为嵌入式半导体解决方案提供商,全球30多个国家拥有超过21,000名工程师,文化以透明、敏捷、全球、创新和创业精神为核心,提供有竞争力的薪酬福利。

职位描述

Job Description Own the system-level and full-chip architecture of next-generation high-end MPU products targeting high-performance applications such as Robotics and Physical AI, industrial networking and control, advanced Vision, multimodal AI processing, and other advanced embedded systems. Define scalable and reusable SoC architectures that integrate heterogeneous compute, Camera/Vision, AI, HMI/Display, memory and interconnect, connectivity, security, safety, and platform-management capabilities into coherent, software-enabled products across multiple market and performance tiers. Translate product strategy, customer use cases, representative workloads, and technology capabilities into architectural decisions that balance performance, power, thermal behavior, area, cost, scalability, software compatibility, implementation feasibility, risk, and time-to-market. Work across a global, multidisciplinary organization spanning Product, business, architecture, HW, SW/FW, verification, implementation, and customer-facing teams. Engage directly with Product Line and Engineering leaders from Director through Vice President level to formulate architecture alternatives, communicate technical and business trade-offs, build alignment, and drive major decisions to timely closure. Principal Accountabilities Own and drive the system-level and full-chip architecture of next-generation MPU products, from early product definition through silicon bring-up and product validation. Develop clear architecture proposals, align technical and business stakeholders, and drive major decisions to timely closure. Translate customer use cases, workloads, market requirements, and product strategy into scalable and reusable SoC architectures across multiple product tiers. Define the full-chip SoC composition, system data and control flows, shared resources, subsystem interfaces, and integration architecture. Define system requirements and allocate performance, power, thermal, memory, bandwidth, latency, QoS, area, and cost budgets across subsystems. Drive convergence and resolve conflicts. Define representative concurrent workloads and use quantitative analysis to identify bottlenecks, validate architectural choices, and drive system-resource convergence. Drive and enable HW/SW co-development through early stakeholder engagement and clear definition of system partitioning, interfaces, requirements, assumptions, and constraints. Drive architecture trade-offs and implementation-feasibility assessments across performance, power, area, cost, software impact, implementation risk, schedule, and technology constraints. Qualifications Essential Extensive experience in the top-level architecture of highly integrated MPU or Application Processor-class SoCs, with demonstrated ownership from product and use-case definition through implementation, silicon bring-up, and product validation. Broad knowledge of heterogeneous compute, memory hierarchy, cache coherency, interconnect, shared resources, high-speed I/O, system control, power management, security, software-visible architecture, and platform integration. Ability to translate customer use cases and concurrent workloads into system data and control flows, requirements, KPIs, resource budgets, and architecture decisions. Experience analyzing system performance through quantitative modeling, identifying bottlenecks and resource constraints, and adjusting the architecture or system configuration accordingly. Ability to incorporate software and firmware requirements, execution constraints, and ecosystem considerations into HW/SW partitioning, interfaces, and SoC architecture decisions. Experience assessing full-chip feasibility and driving trade-offs across performance, power, thermal behavior, area, cost, implementation risk, and schedule. Strong technical leadership and communication skills, with the ability to structure incomplete requirements, develop rigorous proposals, and drive alignment across global teams and senior stakeholders. Desirable Experience with high-performance MPU or application-processor SoCs supporting Robotics, Physical AI, industrial networking and control, advanced Vision, multi-modal AI, or similarly complex workloads. Deep expertise in a major SoC architecture domain, such as compute, memory and interconnect, coherency, system performance, real-time processing, power and thermal architecture, security, or full-chip integration. Experience defining scalable and reusable SoC architectures across product families or performance and cost tiers. Experience with functional-safety or mixed-criticality SoC architecture, including isolation, fault containment, diagnostics, and relevant ISO 26262 or IEC 61508 considerations. Qualifications Essential Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. Desirable Advanced degree, relevant patents, publications, standards participation, or recognized technical leadership in SoC or system architecture. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .