发布于 2026-09-07
英文原文
首席工程师（GaN器件工程师）
Principal Engineer
ルネサス エレクトロニクス
| 职种 | 工程 | 雇用形态 | — |
|---|---|---|---|
| 工作地点 | Zhubei, tw | 薪资 | 面议 |
职位概要
该职位为首席工程师（GaN器件工程师），负责开发用于高效功率转换的氮化镓（GaN）功率器件。候选人需具备GaN器件设计与物理方面的专业知识，以推动高性能/高鲁棒性技术发展，并深入理解陷阱机制及相关表征技术，具备实操经验。主要职责包括：推动对GaN器件物理、电荷陷阱机制及器件可靠性行为的技术理解；定义并评估新器件架构以提升性能、鲁棒性和竞争差异化；在先进器件表征、数据分析和根因调查中提供技术领导，推动性能/良率/可靠性改进；与跨职能团队合作指导技术开发并加速GaN产品商业化。任职要求：电气工程或相关领域博士优先，或硕士学历并具有10年以上半导体器件研发经验，主要聚焦GaN技术；具备表征技术和陷阱分析实操经验，如脉冲I-V（栅极滞后和漏极滞后）、瞬态漏极电流、MOS界面陷阱分析等；具有技术领导力并能有效跨多学科团队工作；中英文流利；需商务出差。加分项：具备TCAD仿真（Sentaurus或Silvaco）经验；熟悉可靠性失效模型和退化机制；熟悉AEC-Q101标准。Renesas为嵌入式半导体解决方案提供商，全球团队超21000名工程师，业务遍及30多个国家，提供汽车、工业、基础设施和IoT领域领先技术。公司文化为TAGIE（透明、敏捷、全球、创新、创业），提供有竞争力的薪酬福利。Renesas为平等机会雇主，致力于多元包容。
职位描述
Job Description Job Summary Principal Engineer, GaN Device Engineer , in charge of development of Gallium Nitride (GaN) power devices for high-efficiency power conversion. The candidate will possess expertise in GaN device design & physics to drive high performance/robustness technology. In addition, have an in-depth understanding of trapping mechanisms and relevant characterization techniques with hands-on experience. With strong communication skills in cross-functional teams to drive development path Key Responsibilities · Drive technical understanding of GaN device physics, charge trapping mechanisms, and device reliability behavior. · Define and evaluate new device architectures to improve performance, robustness, and competitive differentiation. · Technical leadership in advanced device characterization, data analysis, and root-cause investigation to drive performance/ yield/ reliability improvement · Collaborate with cross-functional teams to guide technology development and accelerate commercialization of GaN products. Qualifications [Must] Ph.D. is preferred or M.S. in Electrical Engineering or a related field with 10+ years of semiconductor device R&D experience with major focus on GaN technology. Hands-on experience with characterization techniques and trap analysis: Pulsed I-V (gate-lag and drain-lag), Transient drain current, MOS Interface trap analysis, but not limited as listed. Proven technical leadership and ability to work effectively across multidisciplinary teams. Fluent in both English/Chinese Business travel is required. [Good-to-Have] Experience with TCAD simulation such as Sentaurus or Silvaco. Reliability failure model and degradation mechanism Familiar with AEC-Q101 standard is “plus” Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .