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发布于 2026-10-27 英文原文

DFT负责人

Principal DFT Engineer

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点印度 薪资面议

职位概要

Renesas(瑞萨电子)是全球半导体领导者,年营收超93亿美元(2024年),员工超过22,700人,业务遍及30多个国家。现招聘一名经验丰富的DFT负责人,负责复杂汽车MCU/SoC产品的端到端可测试性设计(DFT)活动。主要职责包括:主导DFT架构与策略制定,定义并实现扫描架构、压缩、存储器BIST、逻辑BIST、边界扫描/JTAG及测试访问架构;推动DFT实现及相关RTL/设计更新;负责DFT验证与仿真,包括测试模式验证、扫描/MBIST连通性、ATPG相关仿真及门级验证;推动ATPG与测试向量生成、验证并向产品与测试工程团队发布量产测试向量;作为与PTE/产品/测试团队的主要技术接口;与设计团队协调DFT需求、测试模式、时钟、复位、电源域、约束及芯片级集成要求;审查DFT覆盖率、向量数量、测试时间及可测试性指标并推动覆盖率缺口闭合;支持硅片启动、向量调试、测试失败及良率相关的DFT调查;负责DFT交付物、评审、签核标准及里程碑跟踪;识别DFT相关技术与进度风险并推动跨职能解决。任职要求:15年以上复杂MCU/SoC器件DFT架构与实现经验;精通扫描插入、扫描压缩、ATPG、MBIST及JTAG/边界扫描;深入理解RTL与门级设计、时钟、复位、电源域及SoC集成;具备DFT仿真、向量验证及门级仿真/调试经验;熟悉ATPG向量生成、故障覆盖率分析及量产向量交付;了解设计DFT与ATE/量产测试之间的接口;具备硅片启动与量产爬坡期间与产品工程及测试工程团队合作经验;熟悉Siemens EDA、Synopsys和/或Cadence的行业标准DFT工具流程;具备较强的问题解决与调试能力,能够跨多个工程组织推动问题解决;能够独立领导DFT活动并与架构、设计、验证、物理设计及产品/测试团队有效沟通。优先条件:汽车MCU或汽车SoC开发经验;了解ISO 26262/功能安全要求及其对测试架构的影响;具备分层测试、嵌入式压缩、逻辑BIST、修复/冗余方案或面向安全的测试特性等先进DFT方法经验;了解量产测试成本、测试时间、覆盖率、诊断要求及良率考量。瑞萨文化以TAGIE为核心:透明、敏捷、全球、创新、创业精神。

职位描述

Company Description Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3 billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies. Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications. Job Description We are looking for an experienced DFT Lead to own end-to-end Design-for-Test activities for complex Automotive MCU/SoC products . The role will drive DFT architecture, implementation, verification, and production-test readiness while working closely with SoC Design, Verification, PTE, Product and Test Engineering teams. Key Responsibilities Own the DFT architecture and strategy for automotive MCU/SoC products from specification through silicon production readiness. Define and implement DFT solutions including scan architecture, compression, memory BIST, logic BIST, boundary scan/JTAG and test access architecture , as applicable. Drive DFT implementation and associated RTL/design updates , working closely with SoC, IP and RTL design teams. Own DFT verification and simulation , including test-mode validation, scan/MBIST connectivity, ATPG-related simulations and gate-level verification. Drive ATPG and pattern generation , validation and release of production-ready test patterns to Product and Test Engineering teams. Act as the primary technical interface with PTE/Product/Test teams for DFT, test-pattern and silicon-test requirements. Work with design teams to define and align DFT requirements, test modes, clocks, resets, power domains, constraints and chip-level integration requirements . Review DFT coverage, pattern count, test time and testability metrics, and drive closure of coverage gaps. Support silicon bring-up, pattern debug, test failures and yield-related DFT investigations . Own DFT deliverables, reviews, sign-off criteria and milestone tracking across the product development lifecycle. Identify DFT-related technical and schedule risks early and drive cross-functional closure. Qualifications Required Skills & Experience 15+ year experience in DFT architecture and implementation for complex MCU/SoC devices . Hands-on expertise in scan insertion, scan compression, ATPG, MBIST and JTAG/boundary scan . Strong understanding of RTL and gate-level design, clocks, resets, power domains and SoC integration. Experience with DFT simulation, pattern verification and gate-level simulation/debug . Experience in ATPG pattern generation, fault coverage analysis and production pattern delivery. Good understanding of the interface between design DFT and ATE/production testing . Experience working with Product Engineering and Test Engineering teams during silicon bring-up and production ramp. Familiarity with industry-standard DFT tool flows from Siemens EDA, Synopsys and/or Cadence . Strong problem-solving and debugging skills with the ability to drive issues across multiple engineering organizations. Ability to independently lead DFT activities and communicate effectively with architecture, design, verification, physical design and product/test teams. Preferred Experience Experience with automotive MCU or automotive SoC development . Exposure to ISO 26262 / functional safety requirements and their impact on test architecture. Experience with advanced DFT methodologies such as hierarchical test, embedded compression, logic BIST, repair/redundancy schemes or safety-oriented test features. Understanding of production test cost, test time, coverage, diagnostic requirements and yield considerations. What We Are Looking For We are looking for someone who can take technical ownership of DFT , not just execute an established flow. The ideal candidate can make architecture decisions, work hands-on through implementation and verification, anticipate downstream production-test requirements, and effectively connect the design organization with Product and Test Engineering . Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .