在招职位 0
订阅提醒 登录
发布于 2026-09-29 英文原文

首席设计验证工程师

Principal Design Verification Engineer

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点Austin, TX, us 薪资面议

职位概要

我们正在招聘一名首席设计验证工程师,为下一代半导体存储接口产品(包括数据缓冲芯片)的验证提供技术领导。该职位将推动复杂数字设计的验证策略与执行,与设计团队紧密合作,确保功能、性能和产品需求得到满足。理想候选人需具备深厚的半导体验证专业知识,精通SystemVerilog和UVM。有DDR或存储经验者优先,但非必需。这是一个在下一代DDR6技术中承担重要技术责任的机会。主要职责:领导模块级和系统级复杂半导体设计的验证策略与执行;定义验证方法学、测试计划、覆盖率策略和验证环境;架构、开发、维护和优化SystemVerilog/UVM测试平台和验证环境;推动测试开发、功能覆盖率、检查器、约束随机验证和覆盖率收敛;对分配的模块、特性和环境从规划到签核承担技术责任;与RTL和设计工程师紧密合作,确保设计满足功能和性能需求且可有效验证;分析规格、设计实现和验证结果,识别功能缺口和设计问题;推动复杂验证失败的调试和解决;开发可扩展和可复用的验证组件、方法学和最佳实践;识别并领导验证效率、质量、性能和复用方面的改进;参与架构、可行性、设计和技术评审;为验证工程师提供技术指导和辅导;作为分配验证方法学和工具的技术专家;向工程领导和项目干系人沟通验证进展、覆盖率、技术风险和就绪状态。必备资格:电气工程、计算机工程、计算机科学或相关技术领域的学士或硕士学位;丰富的半导体设计验证经验,具有复杂验证工作的技术领导经验;专家级SystemVerilog熟练度;丰富的UVM实践经验,包括开发和优化基于UVM的验证环境;具有从设计和产品规格定义验证策略和开发验证计划的经验;在功能验证、约束随机测试、功能覆盖率、检查器、调试和覆盖率收敛方面有丰富经验;在整个验证生命周期中与RTL/设计工程团队紧密合作的经验;具备独立解决复杂验证和设计问题的能力;能够在验证团队内提供技术领导和指导。优先资格:具有DDR、存储接口、存储控制器、数据缓冲器或相关半导体技术经验;具有DDR4和/或DDR5经验;具有复杂高速接口、协议或混合信号半导体产品的验证经验;具有领导验证工作完成覆盖率收敛和签核的经验。Renesas是嵌入式半导体解决方案提供商,以“让我们的生活更轻松”为宗旨。全球团队超过21,000名工程师和问题解决者,遍布30多个国家,为汽车、工业、基础设施和物联网提供世界领先技术。TAGIE文化:透明、敏捷、全球、创新和创业。我们提供有竞争力的福利待遇。Renesas是平等机会和肯定行动雇主,致力于支持多样性。Renesas处理受美国出口管制法规约束的两用技术,可能需要获得美国政府出口许可证。

职位描述

Job Description We are seeking a Principal Design Verification Engineer to provide technical leadership for verification of next-generation semiconductor memory interface products, including data buffer silicon. This role will drive verification strategy and execution for complex digital designs, working closely with design teams to ensure functionality, performance, and product requirements are met. The ideal candidate brings deep semiconductor verification expertise with SystemVerilog and UVM . Previous DDR or memory experience is an advantage, but is not required. This is an opportunity to take significant technical ownership while contributing to next-generation DDR6 technology . Key Responsibilities Lead verification strategy and execution for complex semiconductor designs at the block and system level . Define verification methodologies, test plans, coverage strategies, and verification environments. Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments . Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure. Take technical ownership of verification for assigned blocks, features, and environments from planning through signoff. Work closely with RTL and design engineers to ensure designs meet functional and performance requirements and are effectively verifiable. Analyze specifications, design implementation, and verification results to identify functional gaps and design issues. Drive debugging and resolution of complex verification failures. Develop scalable and reusable verification components, methodologies, and best practices. Identify and lead improvements in verification efficiency, quality, performance, and reuse. Participate in architecture, feasibility, design, and technical reviews. Provide technical guidance and mentorship to verification engineers. Serve as a technical expert for assigned verification methodologies and tools. Communicate verification progress, coverage, technical risks, and readiness to engineering leadership and project stakeholders. Qualifications Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field . Extensive experience in semiconductor design verification , with demonstrated technical ownership of complex verification efforts. Expert-level proficiency with SystemVerilog . Significant hands-on experience with UVM (Universal Verification Methodology) , including development and optimization of UVM-based verification environments. Experience defining verification strategies and developing verification plans from design and product specifications. Strong experience with functional verification, constrained-random testing, functional coverage, checkers, debugging, and coverage closure. Experience partnering closely with RTL/design engineering teams throughout the verification lifecycle. Demonstrated ability to independently solve complex verification and design problems. Ability to provide technical leadership and mentoring within a verification team. Preferred Qualifications Experience with DDR, memory interfaces, memory controllers, data buffers, or related semiconductor technologies . Experience with DDR4 and/or DDR5 . Verification experience with complex high-speed interfaces, protocols, or mixed-signal semiconductor products. Experience leading verification efforts through coverage closure and signoff. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.