SoC数字设计工程师（负责AI辅助工程工具）

Company Description Renesas IC Design Power Division in Zurich develops advanced analog and mixed-signal integrated circuits for power-management and wireless-power applications, delivering complex semiconductor products from architecture and design through silicon validation and volume production. The successful candidate will combine SoC digital design with dedicated technical ownership of internal AI-assisted engineering tools supporting requirements management and specification development. The role includes ongoing software development and maintenance, close collaboration with engineering users, and integration of AI/LLM capabilities into the design flow. Prior experience integrating AI into IC design workflows is an essential requirement for this position. Job Description Key Responsibilities Take technical ownership of internal engineering tools and their existing codebases. Develop enhancements, resolve defects, maintain documentation, manage releases, and provide ongoing support to the engineering team. Develop and validate AI-assisted workflows that translate product requirements into specifications for each engineering discipline. Work with domain experts to preserve traceability to source requirements and manage dependencies and requirement changes. Build automated tests and review workflows to assess the completeness, consistency, and correctness of generated specifications. Ensure outputs can be checked and approved by the responsible engineers. Translate user feedback into tool improvements, maintain integrations with engineering workflows, and evaluate additional AI/LLM applications for requirements analysis, documentation, RTL development, and verification. Translate system and product requirements into digital specifications and micro-architectures. Develop RTL in Verilog/SystemVerilog and integrate embedded processors, memories, peripherals, register maps, and on-chip buses into mixed-signal SoCs. Own digital design activities including lint, CDC/RDC analysis, synthesis, static timing analysis, and low-power design. Support physical implementation and timing closure. Collaborate with system, analog, verification, firmware, and physical design teams on SoC integration, clock and reset architectures, mixed-signal interfaces, design reviews, and verification planning. Support silicon bring-up, laboratory debugging, and product validation through the transition to volume production Qualifications Proven hands-on experience developing and integrating AI-based tools into IC design workflows is required. Candidates must be able to demonstrate implemented solutions in areas such as requirements engineering, specification generation, RTL design, verification, or design-flow automation. MSc or PhD in Electrical Engineering, Microelectronics, Computer Engineering, or a related field. Typically 5+ years of relevant experience in digital IC/SoC design, with experience taking designs from specification through successful silicon. Strong practical experience with Verilog/SystemVerilog, RTL design, and digital subsystem integration. Solid understanding of SoC architectures, including embedded processors, memories, peripherals, register architectures, and on-chip buses such as AMBA AHB/APB. Experience with lint, CDC/RDC, synthesis, static timing analysis, and timing closure, together with an understanding of clock/reset architectures and low-power design techniques. Practical software-development experience and the ability to understand, maintain, and extend an existing application codebase, including version control, testing, debugging, documentation, and release management. Proficiency in Python or comparable programming languages for engineering automation and tool integration; familiarity with Tcl is an advantage. Ability to take ongoing ownership of an internal tool, prioritize improvements with its users, and investigate and resolve software issues. Experience collaborating across analog/mixed-signal, verification, firmware, and physical design teams, including silicon bring-up and debug. Strong analytical and problem-solving skills, clear communication, and the ability to work effectively in an international engineering team. Fluent English. Preferred Experience Mixed-signal SoCs for power-management or wireless-power applications, embedded MCU architectures, and modern EDA design flows. Development of LLM applications using model APIs, retrieval-augmented generation, or tool integration, with evaluation of output quality and reliability. Requirements-management systems, decomposition of product requirements across engineering disciplines, traceability, and change management. AI-assisted software development, including independent review, debugging, and testing of generated code. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .