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发布于 2026-09-23 英文原文

首席产品工程师

Principal Product Engineer

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点Bengaluru, KA, in 薪资面议

职位概要

Renesas(瑞萨电子)是一家全球半导体公司,为汽车、工业、基础设施、数据中心和智能家居等先进应用提供硬件和软件解决方案。IFI组织现招聘首席产品工程师,负责从工程物料规划、认证、特性化、产品发布到量产支持的端到端工作。主要职责包括:主导所分配产品的全生命周期(从概念和首次流片到认证、量产发布、维护和停产);与设计、测试、应用团队协作推动首次流片启动和调试;规划并协调电压、温度和工艺特性化,包括生产限值设定和保护带设置;在Agile等PLM系统中创建和维护产品BOM及生命周期数据;与计划、制造、分包商和运营团队合作消除物料流障碍并弥补进度缺口;按照JEDEC和AEC要求主导认证规划和执行;准备产品发布文档、数据手册合规证据和汽车合规报告;监控生产数据并运用统计分析识别和纠正良率、质量和测试时间缺陷;推动良率提升;优化PAT、SYL、SBL、SPC和处置限值以保护出厂质量;支持晶圆厂转移和BOM变更活动;支持客户退货和RMA调查。技术领导方面需提供技术方向、签署评审、主导跨设计、产品工程、运营、供应商和OSAT团队的技术决策和风险解决,包括DFX议题,需完全独立并被认可为领域专家,能在无直接授权下影响跨职能团队。任职资格:电子工程或工业工程学士学位;至少15年半导体相关经验,涵盖产品工程、NPI、制造、测试;实际理解半导体晶圆制造、封装、测试、认证和量产发布流程;具有管理工程晶圆启动、原型构建、客户样品、库存和产品BOM的经验;熟悉SoC和混合信号器件测试、常见电路构建模块、器件行为和半导体测试方法;熟悉Teradyne J750或Advantest V93000等ATE平台以及示波器、电源和数字万用表等实验室设备;熟悉JEDEC/AEC认证标准、认证硬件/软件和半导体失效分析;具有Agile、PDF Exensio或JMP等PLM和良率管理工具经验;具有与外部晶圆厂、OSAT、分包商和全球分布式产品团队合作的经验;具有失效分析方法经验;能使用数据和统计方法管理良率、质量、周期时间和运营优先级;具有较强的分析、规划、协调和解决问题能力,注重细节,能在进度压力下工作;具有清晰的书面和口头沟通能力,能在无直接授权下影响跨职能团队。Renesas拥有超过21,000名工程师,遍布30多个国家,文化核心为TAGIE(透明、敏捷、全球、创新和创业精神),提供有竞争力的薪酬福利。

职位描述

Company Description Renesas is a global semiconductor company providing hardware and software solutions for advanced automotive, industrial, infrastructure, data-centre and smart-home applications. We are a dynamic, multicultural technology company where employees learn, mentor, innovate and thrive while helping shape what is next in electronics. Job Description IFI organization is seeking a Principal Product Engineer to provide end-to-end ownership from engineering material planning through qualification, characterization, product release and volume-production support. In this role, the principal product engineer acts as the lead within the project and owns the characterization, qualification plan, production release, and industrial activities. Key Responsibilities Own the assigned product lifecycle from concept and first silicon through qualification, production release, sustaining and end of life. Drive first-silicon bring-up and debug with Design, Test, Applications teams. Plan and coordinate voltage, temperature and process characterization, including production limit setting and guard-banding. Create and maintain product BOMs and product lifecycle data in PLM systems such as Agile. Work with planning, manufacturing, subcontractors and operations teams to remove material-flow obstacles and recover schedule gaps. Own qualification planning and execution in accordance with applicable JEDEC and AEC requirements. Prepare product-release documentation, datasheet compliance evidence and automotive compliance reports as applicable. Monitor production data and use statistical analysis to identify and correct yield, quality and test-time deficiencies. Drive yield improvement Optimize PAT, SYL, SBL, SPC and disposition limits to protect outgoing quality Support fab transfer and BOM change activities Support customer-return and RMA investigations by reproducing failures and assessing production test coverage. Technical Leadership Provide technical direction, sign off reviews Lead technical decisions and risk resolution across Design, Product Engineering, Operations, suppliers and OSAT teams including DFX topics Fully independent and recognized as subject-matter-expert Influence cross-functional teams without direct authority and communicate clearly to the stakeholders. Qualifications Bachelor’s degree in electronic engineering or industrial engineering At least 15 years of relevant semiconductor experience spanning product engineering, NPI, manufacturing, test Practical understanding of semiconductor wafer fabrication, assembly, test, qualification and production-release flows. Experience managing engineering wafer starts, prototype builds, customer samples, inventory and product BOMs. Working knowledge of SoC and mixed-signal device testing, common circuit building blocks, device behaviour and semiconductor test methodology. Familiarity with ATE platforms such as Teradyne J750 or Advantest V93000, and with laboratory equipment such as oscilloscopes, power supplies and digital multimeters. Familiarity with JEDEC/AEC qualification standards, qualification hardware/software and semiconductor failure analysis. Experience with PLM and yield-management tools such as Agile, PDF Exensio or JMP. Experience working with external foundries, OSATs, subcontractors and globally distributed product teams. Experience with failure analysis methods Experience using data and statistical methods to manage yield, quality, cycle time and operational priorities. Strong analytical, planning, coordination and problem-solving skills, with attention to detail and the ability to work under schedule pressure. Clear written and verbal communication skills and the ability to influence cross-functional teams without direct authority. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .