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发布于 2026-08-18 英文原文

PAD/PFC逻辑设计工程师

Experienced RTL Design Engineer (3+ Years of Experience)

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点Ho Chi Minh, vn 薪资面议

职位概要

该职位负责为SoC产品设计和实现PAD/PFC逻辑,包括引脚复用、边界扫描、测试功能及I/O控制逻辑,使用公司内部PAD设计工具与方法论。根据设计规格、pinmux定义、PAD-RTL/PAD-IO需求及集成指南实现PAD逻辑,并使用内部工具(如PGA、SCAAPII)生成、集成和验证PAD逻辑,确保规格与生成设计输出的一致性。分析并解决RTL lint、CDC、综合、时序及形式验证工具发现的设计问题。使用Python和Tcl开发自动化脚本以提升设计生产力和流程效率。审查验证、形式验证及签核结果以确保设计质量和完整性。在整个设计生命周期中与验证、DFT、STA、后端及架构团队协作。支持PAD集成、签核活动以及PAD设计方法论和环境的持续改进。要求具备Verilog/SystemVerilog的强RTL设计经验,理解数字设计基础、引脚复用和I/O控制逻辑,良好的Python脚本能力(Tcl为加分项),熟悉SpyGlass Lint & CDC、综合(Genus/DC)和时序分析工具(PrimeTime),了解形式验证(JG-CONN/JG-CSV/JG-FPV)者优先,基本了解DFT、边界扫描和后端实现者优先。需具备较强的自学能力和使用内部设计工具的能力,敏捷的问题解决能力、透明的沟通和协作能力,以及注重设计质量和持续改进的主人翁意识。

职位描述

Job Description Design and implement PAD/PFC logic for SoC products, including pin multiplexing, boundary scan, test functions, and I/O control logic using in-house PAD design tools and methodologies. Implement PAD logic based on design specifications, pinmux definitions, PAD-RTL/PAD-IO requirements, and integration guidelines. Generate, integrate, and validate PAD logic using in-house tools (e.g., PGA, SCAAPII), ensuring consistency between specifications and generated design outputs. Analyze and resolve design issues identified by RTL lint, CDC, synthesis, timing, and formal verification tools. Develop automation scripts using Python and Tcl to improve design productivity and flow efficiency. Review verification, formal verification, and signoff results to ensure design quality and completeness. Collaborate with verification, DFT, STA, backend, and architecture teams throughout the design lifecycle. Support PAD integration, signoff activities, and continuous improvement of PAD design methodologies and environments. Job Requirement: Strong RTL design experience using Verilog/SystemVerilog. Understanding of digital design fundamentals, pin multiplexing, and I/O control logic. Good Python scripting skills; Tcl knowledge is a plus. Experience with SpyGlass Lint & CDC, synthesis (Genus/DC), and timing analysis tools (PrimeTime) Knowledge of formal verification (JG-CONN/JG-CSV/JG-FPV) is an advantage. Basic understanding of DFT, boundary scan, and backend implementation is a plus. Strong self-learning capability and ability to work with in-house design tools. Agile problem-solving, transparent communication, and strong collaboration skills. Ownership mindset with a focus on design quality and continuous improvement. Qualifications Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .