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发布于 2026-09-28 英文原文

高级主任工程师 - MCU设计与架构

Sr Staff Digital Engineer – Microcontroller (MCU) Systems & Architecture

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点Ho Chi Minh, vn 薪资面议

职位概要

该职位为高级主任工程师,加入通用微控制器(MCU)设计与架构团队,负责下一代MCU平台的规格制定、RTL实现、物理综合及全芯片验证,平台集成RISC-V与ARM Cortex-M CPU内核。主要职责包括:将产品需求文档转化为系统控制子系统(SYSSS)、CPU子系统(CPUSS)、外设IP、IOTOP及ChipTop的详细规格;使用Verilog/SystemVerilog进行RTL编码并向中后端团队交付实现指令;使用UVM和SystemVerilog环境制定测试计划并执行单元级与芯片级验证,主导IP、MCU及SoC级根因调试;执行模块级物理综合及顶层技术检查(HLDRC、STAchk、DFTchk);定义并集成基于RISC-V和ARM Cortex-M的MCU子系统,集成WDT、INTC、IIC、SPI、ADC等外设,处理跨时钟域(CDC)与异步传输设计,基于AMBA总线协议(AHB、APB、AXI)设计互连架构。要求具备IP/MCU/SoC开发与调试经验,深入理解RISC-V与ARM Cortex-M架构及MCU外设,精通AMBA协议与CDC技术,熟练掌握Verilog、SVA、SystemVerilog、UVM、C/C++、Perl、Python,并具有Cadence与Synopsys EDA工具链(Xcellium、VCS、Verdi、Spyglass、Design Compiler、Formality、PrimeTime等)实操经验。Renesas为嵌入式半导体解决方案提供商,全球拥有超过21000名工程师,业务覆盖汽车、工业、基础设施与IoT领域,提供有竞争力的薪酬福利,倡导TAGIE文化(透明、敏捷、全球、创新、创业),为平等机会雇主。

职位描述

Job Description Position Overview We are seeking an experienced and visionary Senior Staff Engineer to join our General Purpose Microcontroller (MCU) Design and Architecture team. In this senior technical leadership role, you will lead the specification, RTL implementation, physical synthesis, and full-chip verification of next-generation MCU platforms integrating both RISC-V and ARM® Cortex®-M CPU cores. You will drive the full lifecycle of the System Control Sub-system (SYSSS), CPU Sub-system (CPUSS), Peripheral IPs, IOTOP, and ChipTop design and verification, bridging architecture definitions with silicon implementation, advanced debugging, and technology verification. Key Responsibilities SYSSS, CPUSS, Peripheral IP, IOTOP & ChipTop Design & Verification (Full Flow): Specification & Architecture: Translate high-level Product Requirement Documents (PRDs) into comprehensive Target & Detail Specifications for System Control Sub-system (SYSSS), CPU Sub-system (CPUSS), Peripheral IPs, IOTOP, and ChipTop modules. RTL Implementation & Hand-off: Perform RTL coding (Verilog / SystemVerilog) for SYSSS, CPUSS, Peripheral IPs, IOTOP, and ChipTop. Author and deliver clear implementation instructions to MiddleEnd and BackEnd (Physical Design) teams. Design Verification & Debugging: Create test plans and execute Unit-Level Verification (UT) and Chip-Level / Top-Level Verification (CT) using UVM and SystemVerilog environments. Lead root-cause debugging across IP, MCU, and SoC levels. Physical Synthesis & Technology Verification: Run module-level physical synthesis and perform top-level technology checks, including High-Level DRC (HLDRC), Static Timing Analysis checks (STAchk), and Design-for-Testability checks (DFTchk) at SYSSS and ChipTop levels. Architecture & Subsystem Integration: Define and integrate MCU subsystems around RISC-V and ARM Cortex-M architectures. Integrate key peripherals (WDT, INTC, IIC, SPI, ADC, etc.) and handle clock domain crossing (CDC) / asynchronous transfer designs across clock and reset boundaries. Drive interconnect architecture based on AMBA bus protocols (AHB, APB, AXI). Technical Expertise & Domain Knowledge IP / MCU / SoC Debugging: Strong hands-on experience in IP, MCU, and SoC level development with expert-level debugging skills across front-end RTL, simulation, and post-synthesis environments. Processor Cores & Peripherals: Deep understanding of RISC-V and ARM Cortex-M CPU architectures and common MCU peripherals (e.g., Watchdog Timers [WDT], Interrupt Controllers [INTC], I2C/IIC, SPI, ADC). Bus Protocols & Interconnects: Thorough technical knowledge of AMBA protocols (AHB, APB, AXI, etc.). Asynchronous Transfer & CDC: In-depth knowledge of Clock Domain Crossing (CDC) and Asynchronous Transfer Design techniques to prevent metastability in multi-clock MCU systems. HDL & Programming Languages: High proficiency in industry-standard languages: Hardware / Verification: Verilog, SVA, SystemVerilog, UVM Embedded Software / Verification: C, C++ Scripting & Automation: Perl, Python EDA Toolchains: Hands-on experience with industry-standard Cadence and Synopsys EDA tools, including: Simulators & Debuggers: Xcellium, VCS, SimVision, Verdi RTL Lint, CDC & Static Analysis: Spyglass, and related static check tools. Synthesis and netlist check: Design compiler, Formality, STAcheck (PrimeTime), HLDRC, DFTcheck Design & Verification Flow: Full-flow experience from PRD specification writing to RTL coding, UT/CT testbench creation, verification checklist, coverage. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .