在招职位 0
订阅提醒 登录
发布于 2026-11-09 英文原文

半导体测试工程师

Sr Test Engineer

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点日本东京小平市 薪资面议

职位概要

该职位为位于日本东京小平市的半导体测试工程师,负责先进半导体产品量产测试方案的开发与部署,覆盖测试策略、硬件开发、特性分析、认证、量产发布及持续改进全流程。主要职责包括:制定测试策略、测试计划、DFT需求及ATE方案;使用C/C++开发、调试和优化ATE测试程序,关注测试覆盖率、测量精度、测试时间、多工位效率、良率及测试成本;为功率IC和模拟/混合信号产品开发稳健测试方案,包括大电流测试技术;设计调试负载板、DUT接口板、探针接口等测试硬件;通过硅前仿真验证测试方案;运用模拟与混合信号工程知识排查器件、ATE、测试程序、硬件及制造环境间的复杂问题;执行ATE与台式机相关性、尖峰检查、GR&R、保护带分析及测试限值验证;推动测试时间、良率及成本优化;制定里程碑与风险缓解计划;与全球团队协作并指导其他工程师。要求电气/计算机/电子工程本科或同等经验,4年以上半导体测试经验,熟悉Teradyne ETS-88/ETS-800、Cohu DiamondX等ATE平台,精通模拟混合信号电子学、测量精度、信号完整性、接地与供电,具备原理图与PCB设计工具经验,了解量产测试方法,英语流利,日语优先。公司提供有竞争力的薪酬与完善福利。

职位描述

Job Description We are seeking an experienced Semiconductor Test Engineer to join our engineering team in Kodaira, Tokyo, Japan . This is a hands-on technical role with the opportunity to develop and deploy production test solutions for advanced semiconductor products. You will work across the full test-development lifecycle, from test strategy and hardware development through characterization, qualification, production release, and continuous improvement. The role has a strong focus on quality, manufacturability, test coverage, test efficiency, yield, and cost of test , while providing opportunities to solve challenging technical problems and collaborate with engineering and manufacturing teams around the world. Key Responsibilities Develop and implement semiconductor test strategies, test plans, DFT requirements, test methods, and ATE solutions for wafer sort/probe, characterization, qualification, and final production test. Develop, debug, optimize, and maintain ATE test programs using C/C++ and platform-specific programming environments , with focus on test coverage, measurement accuracy, test time, multisite efficiency, yield, and cost of test. Develop robust test solutions for power ICs and analog/mixed-signal semiconductor products , including appropriate techniques for high-current testing. Design and debug test hardware , including load boards, DUT interface boards, probe interfaces, and associated circuitry. Validate test solutions through pre-silicon simulation to verify test methods, test-program functionality, and ATE implementation prior to first silicon. Apply strong analog and mixed-signal engineering fundamentals to troubleshoot complex interactions among the device, ATE, test program, test hardware, and manufacturing environment . Perform test-method validation and production-readiness activities, including ATE-to-bench correlation, spike-check, characterization, GR&R, guardband analysis, and test-limit validation . Drive improvements in test time, multisite efficiency, yield, test robustness, and cost of test . Establish test-development milestones, schedules, dependencies, technical risks, and mitigation plans , and communicate progress and issues clearly to project stakeholders. Collaborate with product, design, DFT, systems, manufacturing, quality, and other engineering teams across Japan and global locations. Provide technical guidance and mentoring to other engineers and contribute to continuous improvement of test engineering methods and processes. Qualifications Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related technical field , or equivalent relevant engineering experience. 4+ years of semiconductor test engineering experience , preferably involving analog, mixed-signal, power, or automotive semiconductor products. Hands-on experience developing and debugging ATE test programs and test hardware for wafer sort/probe and/or final production test. Experience with semiconductor ATE platforms such as Teradyne ETS-88/ETS-800, Cohu DiamondX, or equivalent platforms . Strong understanding of analog and mixed-signal electronics , including measurement accuracy, signal integrity, grounding, power delivery, and troubleshooting techniques. Experience with power IC or other high-current semiconductor devices and associated test methodologies. Experience with pre-silicon simulation or simulation-based validation of semiconductor test methods and ATE test programs is an advantage. Experience with schematic capture and PCB design tools such as Altium Designer, Cadence/OrCAD, or equivalent . Working knowledge of semiconductor production-test methodologies, including characterization, qualification, correlation, GR&R, sampling, multisite testing, production release, test-time optimization, yield improvement, and cost-of-test reduction . Strong analytical and troubleshooting skills, with the ability to independently investigate complex technical issues and drive them toward resolution. Strong communication and collaboration skills, with the ability to work effectively in a multicultural and geographically distributed engineering organization . Experience with automotive semiconductor products and associated qualification or production requirements is an advantage. Language Skills English: Ability to communicate effectively in a global engineering environment Japanese: Preferred but not required. Japanese proficiency is an advantage for collaboration with local teams in Japan. Additional Information ルネサスは、「To Make Our Lives Easier(人々の暮らしをより豊かで快適にする)」というPurposeのもと、組込み半導体ソリューションを提供するグローバル企業です。世界30か国以上で活躍する21,000人を超えるエンジニアや課題解決のプロフェッショナルとともに、自動車、産業、インフラ、IoT分野における世界最先端のテクノロジー開発に携わり、より安全で、健康的で、環境にやさしく、スマートな未来の実現に貢献しています。 ルネサスでは、「TAGIE(Transparent、Agile、Global、Innovative、Entrepreneurial)」を企業文化の中核としています。TAGIEは、私たちの働き方や成長のあり方、そしてPurposeの実現に向けた取り組みを支える共通の価値観です。この協調的な精神と挑戦するマインドセットが、半導体技術を通じた産業の変革と、世界中の人々の暮らしへの貢献を可能にしています。 私たちは、競争力のある報酬制度に加え、充実した福利厚生をご用意しています。福利厚生の詳細については、選考プロセスの中でご案内いたします。 私たちとともに未来を創造する挑戦に、ぜひ参加しませんか。皆さまからのご応募をお待ちしております。