发布于 2026-10-20
英文原文
掩膜设计师
Mask Designer 5
ルネサス エレクトロニクス
| 职种 | 工程 | 雇用形态 | — |
|---|---|---|---|
| 工作地点 | 美国北卡罗来纳州三角研究园或佛罗里达州棕榈湾 | 薪资 | 面议 |
职位概要
Renesas抗辐射精密设计团队招聘经验丰富的掩膜设计师,工作地点为美国北卡罗来纳州三角研究园或佛罗里达州棕榈湾。该职位负责为面向太空市场的抗辐射产品开发团队创建顶层和单元级版图,涵盖电源管理产品、精密模拟产品、数字核心版图以及新工艺变体的数字库开发。候选人需使用Cadence工具集,并与电路设计师、版图设计师和CAD团队协作。职责包括:从顶层版图布局规划到宏/模块级布线等多层级工作;与电路设计师紧密合作构建物理设计布局规划并创建封装键合图;创建高性能定制模拟和混合信号单元版图并验证;在满足电路设计要求的约束下完成物理版图设计;验证物理版图设计以满足电路设计和工艺要求;执行掩膜数据发布和归档;使用新工具和方法,并与CAD/CAE合作提升版图设计质量和效率。资格要求:至少十五年模拟、电源或混合信号IC版图经验;熟悉IC版图方法学、流程及Cadence Virtuoso版图物理验证等CAD工具;具备电路和版图设计相关的电子学基本原理;有BCD和SOI工艺经验;良好的沟通能力;熟悉器件物理者优先。Renesas提供有竞争力的薪酬福利,具体信息将在招聘过程中提供。
职位描述
Job Description The Rad Hard Precision Design Group is seeking an experienced mask designer to join the team in either the Research Triangle Park, NC or the Palm Bay, FL locations. The purpose of this position is to create top-level and cell-level layouts for our Rad Hard product development team targeted toward Space markets. The Rad Hard developments include power management products, precision analog products and digital core layouts along with digital library development for new process variants. The candidate will utilize the Cadence tool set and requires interaction with circuit designers, layout designers, and CAD team. Responsibilities: Work at multiple levels of hierarchy from top-level layout floor planning to macro/block level routing Work closely with circuit designers to build physical design floorplan and create package bond diagrams Create high performance custom analog and mixed signal cell layout and verification Complete the physical layout design with the constraints of circuit design requirements Verify the physical layout design to meet both circuit design requirements and process requirements Execute mask data release and archiving Use new tools and methods and work with CAD/CAE to improve layout design quality and efficiency Qualifications Minimum fifteen years experience working with analog, power or mixed signal IC layouts A good working knowledge of IC layout methodologies, flows and CAD tools such as Cadence virtuoso layout physical verification Basic understanding of electronic principles dealing with circuit and layout design Previous experience with BCD and SOI processes. Good communication skills Familiar with device physics is preferred Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.