数字设计工程师（电源管理ASIC）

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Job Purpose and Dimensions: Develop micro-architecture and front-end digital design deliverables from concept to silicon with minimal supervision Develop digital functional blocks for various power management ASICs Principal Accountabilities: Lead optimized digital blocks design meeting functional and low power constraints and ensure spec compliance. Must have experience of defining Digital/Analog boundaries and digital design scope for Power Management ICs/Analog intensive ICs. Must have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc. Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner Should be able to lead/collaborate for Logic Synthesis, Formal verification, Power estimation and STA. Should have experience of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions, DFT architecture and integration. · Should be an expert of one or more Power Chip Communication I/Ps and protocols e.g. I2C, PMBUS etc. Verification test planning, feature extraction and verification test case development. Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc. · Support DFT strategy and implementation. Interface with P & R for digital hand-off and post layout verification. Perform physical silicon device area and power evaluation where necessary. Produce high quality documentation for owned blocks. Develop work-around solutions where necessary to overcome device errata including documentation. Key Performance Measures: Micro-architecture, functional, test plan specification delivered according to project schedule RTL coding using Verilog/System Verilog First time right success rate Pro-actively taking ownership of responsibilities. Deliver work in the agreed timescales as set by program schedule for all assigned tasks. Knowledge, Skills and Experience: Experience in Logic design /micro-architecture / RTL coding. · Must have hands on experience with Power product design, synthesis and timing analysis for complex Digital Circuits. Experience in Verilog/System-Verilog is a must. Experience working in semiconductor ideally PMIC with focus on mixed signal integrated circuits · Hands on experience developing block and top-level timing constraints for STA and P & R sign off Understanding of design constraints and synthesis scripts Work independently on straightforward tasks, with little direction from manager · Ability to propose innovative solutions Results-oriented and able to deliver on-time under a tight schedule Cross cultural awareness and sensitivity Proactive attitude about own role and contribution to company goals Ability to work both independently and part of a team Excellent command of verbal and written English Concise and precise communication and interpersonal skills within multi-site and multi-cultural environment Qualifications Degree level qualification in Electronics Engineering Key Relationships: Design team, in particular TPL (Technical Project Leader) and digital leads/manager Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .