发布于 2026-08-25
英文原文
高级数字验证工程师
Senior Digital Verification Engineer
ルネサス エレクトロニクス
| 职种 | 工程 | 雇用形态 | — |
|---|---|---|---|
| 工作地点 | Kallithea, Athens, gr | 薪资 | 面议 |
职位概要
该职位招聘一名经验丰富的高级数字验证工程师,负责复杂IC模块与系统的端到端验证。主要职责包括:制定并执行全面的验证策略与测试计划,从零搭建基于UVM的验证环境;通过约束随机测试、基于断言的验证(SVA)及形式化方法推动功能覆盖率和代码覆盖率收敛;在设计周期早期评审设计规格以提升其质量与可验证性;与全球架构、设计及软件团队协作,优化软硬件划分与系统级验证;指导初级工程师、主持设计/验证评审并优化自动化流程;参与第三方VIP与工具评估,主导自研/采购决策。任职要求:具备丰富的ASIC/IC数字验证经验,精通SystemVerilog与UVM;能够独立从零搭建UVM测试平台并将规格转化为完整验证环境;熟练使用行业标准仿真与管理工具(如Cadence Xcelium、eManager/vManager)及Verilog、VHDL、SystemVerilog;扎实掌握功能验证、ABV、形式化验证与回归框架;具备中高级数字设计能力;优秀的英语沟通能力与推动技术决策的魄力。Renesas为嵌入式半导体解决方案提供商,全球逾21000名工程师,业务覆盖汽车、工业、基础设施与IoT领域,提供有竞争力的薪酬福利,倡导透明、敏捷、全球化、创新与创业精神的文化,是平等机会雇主。
职位描述
Job Description We are seeking an experienced Senior Digital Verification Engineer to lead end‑to‑end verification of complex IC blocks and systems. Key Responsibilities Define Strategy & Ownership: Architect and execute comprehensive verification strategies, test plans, and implement UVM-based environments from scratch. Verification Closure: Drive functional and code coverage to closure, utilizing constrained-random testing, assertion-based verification (SVA), and formal methods to prove design correctness. Specification Quality: Review design specifications early in the cycle to improve their quality, clarity, and "fitness for verification." Cross-Functional Collaboration: Partner with global architecture, design, and software teams to optimize hardware/software partitioning and system-level verification. Technical Leadership: Mentor and tutor junior engineers, champion design/verification reviews, and optimize automation flows for reusability and performance. Make/Buy Decisions: Participate in evaluating third-party VIP and tools, steering make/buy choices to ensure maximum engineering efficiency. Qualifications Experience: Extensive proven experience in ASIC/IC digital verification with strong mastery of SystemVerilog and UVM. Strong Technical capabilities : Demonstrated ability to independently set up a UVM testbench from scratch, translating a specification into a final full verification Environment. Tools & Languages: Proficiency with industry-standard simulators and management tools (e.g., Cadence Xcelium, eManager/vManager) along with Verilog, VHDL, and SystemVerilog. Methodologies: Solid grounding in Functional Verification, ABV, Formal Verification, and regression frameworks. Design Skills: Intermediate to advanced digital design skills, allowing for deep technical alignment with design and architecture teams. Communication: Excellent interpersonal skills and strong proficiency in English (written and verbal), with the assertiveness to effectively guide technical decisions. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .