发布于 2026-10-13
英文原文
模拟IC版图工程师(F/M/D)
(Senior) Layout Engineer (f/m/d)
ルネサス エレクトロニクス
| 职种 | 工程 | 雇用形态 | — |
|---|---|---|---|
| 工作地点 | 德国德累斯顿、慕尼黑或宾根 | 薪资 | 面议 |
职位概要
该职位隶属于汽车传感器业务部门,负责传感器ASIC、传感器ASSP、位置传感器、LiDAR ASIC及环境传感器的开发。工作地点为德国德累斯顿、慕尼黑或宾根。主要职责包括:按照Renesas产品开发流程和行业最佳实践创建模块级和顶层版图设计;负责多次流片的IC及测试结构版图设计;使用参数化版图、LVS、DRC和DFM等标准设计流程高效准确地实现芯片级版图要求;支持模块级和顶层规格制定;实现面向良率和可制造性的模拟版图设计;确保模块级和顶层DRC与LVS检查通过;优化硅片成本并交付一次成功的优化版图。任职要求:电气工程、电子、微电子、微系统或相关专业学位;具备半导体器件物理和微电子基础知识;熟悉Cadence Virtuoso及其他Cadence工具;具有使用Calibre DRC和LVS进行版图验证的经验;具有使用Calibre和Cadence工具进行寄生提取及分析的经验;具备自我驱动力、开放思维和团队合作能力;良好的书面和口头沟通及技术报告能力;流利英语,德语能力为加分项。Renesas提供具有竞争力的薪酬福利,具体信息将在招聘过程中提供。
职位描述
Job Description To further strengthen our Automotive Sensors business comprising Sensor ASICs, Sensor ASSPs, Position Sensors, LiDAR ASICs and Environmental Sensors, we are currently looking for an Analog IC Layout Engineer (F/M/D) to join our engineering team in Dresden, Munich or Bingen am Rhein, Germany, for developing our new and next generation ICs, integrated sensors, innovations, power and mixed signal technologies besides supporting modifications to existing products. Your Role: Create block-level and top-level layout design and implement them according to Renesas product development process following best practices from the industry Own layout design for multiple tape outs of ICs and test structures Implementation of the chip level layout requirements with efficiency and accuracy using industry standard design flows - parameterized layout, LVS, DRC and DFM Support block-level and top-level specifications Implement analog layout dependent design for yield and manufacturability Ensure block- and top-level Design Rule Checks (DRC) and Layout versus Schematics Checks (LVS). Ensure optimized silicon COGS and deliver optimized layouts that are first time right Qualifications Your Profile: Degree in Electrical Engineering, Electronics, Microelectronics, Microsystems or similar Fundamental knowledge on Semiconductor Device Physics and Microelectronics is required Experience with Cadence Virtuoso and other Cadence tools Experience with layout verification using Calibre DRC and LVS layout verification tools Experience with parasitic extraction using Calibre and Cadence tools and their analysis. High level of self-motivation, drive, open-mindedness and teamwork skills are desired Good communication and technical reporting skills, both written and oral Fluent English and German knowledge would be a plus Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .