在招职位 0
订阅提醒 登录
发布于 2026-09-17 英文原文

模拟与混合信号设计验证工程师(负责人)

Verification Staff Engineer - Analog Mixed-Signal

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点Kodaira, jp 薪资面议

职位概要

该职位负责执行并主导指定的设计验证活动,支持首次流片成功,并确认性能、功耗和进度要求合规。负责或参与集成电路及子系统的模拟与混合信号验证,与AMS DV团队成员及本地合同验证资源协作。参与混合信号IP验证策略,使用面向对象编程原则和方法(包括UVM)实现验证IP。工作内容包括验证规划、维护、特性提取、验证测试、覆盖率和检查器开发;开发高效、可复用的先进验证环境和测试平台结构;参与与模拟/数字设计、系统、测试、验证和确认团队的技术评审;能够调试RTL以理解设计意图,并与跨职能团队接口协作。需为验证团队成员提供技术指导和支持。关键绩效指标包括:在约定项目进度内交付高质量验证计划、环境、测试、检查器和覆盖率;识别验证风险并及时沟通问题,参与有效缓解计划;根据批准规范和覆盖率目标实现验证完整性;开发可复用验证组件并提高验证效率;提供清晰技术文档并与团队分享知识;与设计、系统、测试、验证和确认等工程师有效协作;在工作中体现Renesas精神。任职要求:5年以上先进验证方法学经验,主导过复杂数字和混合信号设计的验证;电气工程、电子、计算机工程、计算机科学或同等学位;扎实的模拟和混合信号电路概念与拓扑基础;具有混合信号验证环境、仿真和回归工具经验,如Cadence Virtuoso、xCelium、Incisive、vManager、IMC;能够阅读模拟原理图并提取相关主要功能;熟悉基于Verilog的RTL编码和ASIC设计方法;精通SystemVerilog和先进验证方法学,包括断言、约束随机化、指标驱动验证和UVM;熟悉使用SystemVerilog(RNM)和VerilogAMS进行模拟模块行为建模;具有混合信号模块建模经验,包括偏置网络、功率调节器、带隙、简单放大器、比较器、数据转换器、混频器、多路复用器、开关、功率转换器等;有功率转换器建模经验者优先;良好的UNIX shell脚本、Perl和TCL脚本知识;具有编写验证计划和测试平台开发、仿真和调试的 proven 经验。通用要求:在多站点和多文化环境中具备简洁主动的沟通能力;能够清晰传达技术建议并基于技术事实建立共识;能够在需要时支持与内部利益相关者、客户或合作伙伴的技术讨论;对解决方案负责并推动实现,自我激励;寻求自身和Renesas工作实践的持续改进;良好的分析和解决问题能力;结果导向,能在紧张进度压力下按时交付;能够提出创新解决方案;跨文化意识和敏感性。Renesas是一家全球嵌入式半导体解决方案提供商,以“To Make Our Lives Easier”为宗旨,在30多个国家拥有超过21,000名工程师和问题解决专家,致力于汽车、工业、基础设施和IoT领域的前沿技术开发。公司以TAGIE(Transparent、Agile、Global、Innovative、Entrepreneurial)为核心文化,提供有竞争力的薪酬和福利。

职位描述

Job Description Principal Accountabilities: Execute and own assigned design verification activities that support first-pass silicon success and confirm compliance with performance, power, and schedule requirements. Own or contribute to analog and mixed-signal verification of integrated circuits or subsystems. Collaborate with AMS DV team members and local contract DV resources on assigned verification activities. Contribute to verification strategies for mixed-signal IPs and implement verification IP using object-oriented programming principles and methodologies, including UVM. Verification planning, maintenance, feature extraction, verification tests, coverage and checker development. Develop efficient, reusable state-of-the-art verification environments and testbench structures. Participate in technical reviews with analog and digital design, systems, test, validation, and verification teams. Able to debug the RTL for design intent and interface with cross-functional teams and collaboration in all verification related activities. Provide technical guidance and support to verification team members within assigned areas of expertise. Key Performance Measures: Deliver high-quality verification plans, environments, tests, checkers, and coverage within agreed project schedules. Identify verification risks, communicate issues promptly, and contribute to effective mitigation plans. Achieve verification completeness against approved specifications and coverage goals. Develop reusable verification components and improve verification efficiency. Provide clear technical documentation and share relevant knowledge with the verification team. Collaborate effectively with design, systems, test, validation, and other verification engineers. Demonstrate the Spirit of Renesas in all aspects of work. Qualifications Knowledge, Skills and Experience: The ideal candidate has an experience of 5+ years in advanced verification methodologies, owning the verification of complex digital and mixed signal designs Degree level qualification in electrical engineering, electronics, computer engineering, computer science, or equivalent. Strong fundamentals in analog and mixed signal circuit concepts and topologies. Experience working with mixed signal verification environment, simulation, and regression tools such as Cadence Virutuoso, xCelium, Incisive, vManager, IMC Ability to read analog schematics and extract related main functionality. Familiar with Verilog based RTL coding and ASIC design methodology. Strong proficiency in SystemVerilog and advanced verification methodologies, including assertions, constrained randomization, metric-driven verification, and UVM. Familiar with behavioral modelling of analog blocks using System Verilog (RNM) and VerilogAMS. Experience in modelling mixed signal blocks including biasing networks, power regulators, bandgaps, simple amplifiers, comparators, data converters, mixers, multiplexers, switches, power converters, etc. Experience modelling power converters is desired. Good knowledge of UNIX shell scripting, Perl and TCL scripting. Proven experience in writing verification plans and test bench development, simulation and debugging. General: Concise and proactive communication skills within a multi-site and multi-cultural environment Ability to communicate technical recommendations clearly and build alignment based on technical facts. Ability to support technical discussions with internal stakeholders, customers, or partners when required. Takes responsibility for solutions and makes them happen, self-motivated. Looks for continuous improvement in own and Renesas work practices. Good analytical and problem-solving skills. Results-oriented and able to deliver on-time under tight schedule pressure. Ability to propose innovative solutions. Cross cultural awareness and sensitivity Additional Information ルネサスは、「To Make Our Lives Easier(人々の暮らしをより豊かで快適にする)」というPurposeのもと、組込み半導体ソリューションを提供するグローバル企業です。世界30か国以上で活躍する21,000人を超えるエンジニアや課題解決のプロフェッショナルとともに、自動車、産業、インフラ、IoT分野における世界最先端のテクノロジー開発に携わり、より安全で、健康的で、環境にやさしく、スマートな未来の実現に貢献しています。 ルネサスでは、「TAGIE(Transparent、Agile、Global、Innovative、Entrepreneurial)」を企業文化の中核としています。TAGIEは、私たちの働き方や成長のあり方、そしてPurposeの実現に向けた取り組みを支える共通の価値観です。この協調的な精神と挑戦するマインドセットが、半導体技術を通じた産業の変革と、世界中の人々の暮らしへの貢献を可能にしています。 私たちは、競争力のある報酬制度に加え、充実した福利厚生をご用意しています。福利厚生の詳細については、選考プロセスの中でご案内いたします。 私たちとともに未来を創造する挑戦に、ぜひ参加しませんか。皆さまからのご応募をお待ちしております。