发布于 2026-11-05
英文原文
资深CAD物理设计方法工程师
Staff CAD Layout Automation and Methodology Engineer
ルネサス エレクトロニクス
| 职种 | 工程 | 雇用形态 | — |
|---|---|---|---|
| 工作地点 | 印度 | 薪资 | 面议 |
职位概要
瑞萨电子是全球领先的半导体公司之一,致力于打造更安全、健康、环保和智能的世界。PDK团队现招聘一名常驻印度的资深CAD物理设计方法工程师,以加强对业务部门的支持。主要职责包括:为模拟、混合信号和数字设计团队开发、集成、维护和部署PDK物理设计组件/IP及方法,覆盖成熟和先进工艺节点;开发、调整、增强并发布PDK物理设计流程和设计支持资料;定义并维护物理设计方法、配置及针对特定技术和产品需求的定制选项;开发和维护与工艺相关的版图结构、参考组件及支持工具;将代工厂技术要求转化为稳健可复用的PDK物理设计流程和解决方案;与代工厂、EDA供应商、PDK及设计团队协作,解决物理设计需求和集成问题。任职要求:熟悉CMOS、平面和FinFET基础知识、半导体技术和IC设计,电气/电子工程、半导体物理或相关专业背景;深入理解IC物理设计和版图方法,包括工艺相关版图要求、芯片级集成和流片考虑;具有使用Virtuoso环境开发、集成和维护物理设计工具和流程的经验;具备跨版图、EDA和设计流程环境的调试和问题解决能力;能够解读代工厂技术文档和设计需求,并使用原生EDA供应商工具或自定义工具转化为流程;熟悉UNIX/Linux环境、Shell脚本,精通Python、Perl;具备丰富的Cadence SKILL编程经验;有开发自动化与生产力工具支持设计团队的经验者优先;具备良好的沟通和协作能力;有全芯片版图/物理设计开发和流片背景者优先。瑞萨提供具有竞争力的薪酬福利,具体信息将在招聘过程中提供。
职位描述
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Job Summary: The PDK team is looking for an experienced Staff CAD Physical Design Methodology Engineer based out of India region to enhance the team’s support for our business units. Develop, integrate, maintain and deploy PDK Physical Design components/IP and methodologies for Analog, Mixed-Signal and Digital design teams across mature and advanced technology nodes. Job Description: Develop, adapt, enhance and release PDK Physical Design flows and design enablement collateral for internal customers. Define and maintain physical-design methodologies, configurations and customization options for technology and product-specific requirements. Develop and maintain technology-dependent layout structures, reference components and supporting utilities. Translate foundry technology requirements into robust and reusable PDK Physical Design flows and solutions. Collaborate with foundries, EDA vendors, PDK and design teams to address physical-design requirements and integration. Qualifications Good knowledge of CMOS , planar and finfet fundamentals, semiconductor technology and IC design, with a background in Electrical/Electronics Engineering, Semiconductor Physics or a related discipline. Strong understanding of IC physical design and layout methodologies, including technology-dependent layout requirements, chip-level integration and Tape-Out considerations. Demonstrable experience in developing, integrating and maintaining tools , flows for Physical design using Virtuoso environment Strong debugging and problem-solving skills across layout, EDA and design-flow environments. Ability to interpret foundry technology documentation and design requirements and translate them into flows using native EDA vendor tools or custom tools Good knowledge of UNIX/Linux environments, shell scripting, with proficiency in Python, Perl Strong Cadence SKILL programming experience Experience developing automation and productivity tools for supporting design teams is highly desirable. Good communication and collaboration skills for working with foundries, EDA vendors, CAD/EDA teams and IC design teams. Background in Full chip layout/physical design development and Tapeout is highly desired Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .