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发布于 2026-11-06 英文原文

缺陷量测主任工程师

Staff Defect Metrology AI/ML Engineer

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点Goleta, CALIFORNIA, us 薪资该职位的预期年薪范围为120,000美元至160,000美元。该职位还可获得奖金机会。

职位概要

我们正在为MOCVD团队招聘一名积极主动的缺陷量测主任工程师。该职位将在半导体缺陷检测、数据分析以及先进缺陷检测与分类能力开发方面提供技术领导。理想候选人需具备半导体量测实操经验,并精通Python、数据分析、图像处理及AI/ML,以提升产品质量、工艺控制和制造良率。主要职责包括:开发图像处理算法和AI/ML模型以检测、分类和量化颗粒、凹坑、划痕等半导体缺陷;分析晶圆检测、量测和MOCVD工艺的大数据集,识别趋势、相关性、异常和根本原因;使用Python、SQL、JMP、Excel等开发自动化分析和可视化工作流;将 incoming 衬底缺陷与外延缺陷关联,开发数据驱动的衬底质量筛选方法;整合缺陷、工艺、设备和晶圆级数据;与工艺、设备及开发工程师合作;改进检测方法、算法、校准、统计指标和缺陷分类策略;确保缺陷量测系统及数据的准确性、可重复性和完整性;应用DOE、SPC、统计建模和数据可视化支持工艺改进;向工程团队、管理层、供应商和客户传达技术发现和建议。任职资格:工程、科学、数据科学、计算机科学或相关领域学士学位+5年以上、硕士学位+3年以上或博士学位;具备半导体缺陷检测、量测、良率工程、制造分析、图像分析或相关领域经验;强大的数据分析和编程能力, preferably Python和SQL;具有将AI/ML、计算机视觉、统计学习或高级分析应用于工程问题的经验;熟悉pandas、NumPy、scikit-learn、OpenCV、PyTorch或TensorFlow者优先;优秀的组织能力、注重细节、分析和解决问题的能力;强大的团队合作和协作能力。优先条件:具有基于AI/ML的晶圆缺陷检测或分类经验;具有开发自动化数据管道、仪表板或制造分析工具的经验;具有KLA Candela或Nanotronics等光学晶圆检测系统经验;了解半导体材料、外延生长和材料表征;具有DOE、SPC、工艺能力和统计建模经验;熟悉洁净室协议和半导体晶圆处理。申请人必须目前有权在美国全职工作,公司无法赞助工作签证。

职位描述

Job Description We are seeking a highly motivated Staff Engineer, Defect Metrology to join our MOCVD team. This role will provide technical leadership in semiconductor defect inspection, data analytics, and development of advanced defect detection and classification capabilities. The ideal candidate combines hands-on semiconductor metrology experience with strong skills in Python, data analysis, image processing, and AI/ML to improve product quality, process control, and manufacturing yield. Key Responsibilities: Develop image-processing algorithms and AI/ML models to detect, classify, and quantify semiconductor defects such as particles, pits, and scratches. Analyze large datasets from wafer inspection, metrology, and MOCVD processes to identify trends, correlations, anomalies, and root causes. Develop automated analysis and visualization workflows using Python, SQL, JMP, Excel, and related tools. Correlate incoming substrate defects with epitaxial defects and develop data-driven methods for substrate quality screening. Integrate defect, process, equipment, and wafer-level data to improve understanding of defect mechanisms and yield drivers. Partner with process, equipment, and development engineers to correlate defect excursions with process changes and equipment events. Improve inspection methodologies, algorithms, calibrations, statistical metrics, and defect classification strategies. Ensure the accuracy, repeatability, and integrity of defect metrology systems and associated data. Apply DOE, SPC, statistical modeling, and data visualization to support process improvement. Communicate technical findings and actionable recommendations to engineering teams, management, vendors, and customers. Qualifications Required BS with 5+ years, MS with 3+ years, or PhD in Engineering, Science, Data Science, Computer Science, or a related field. Experience in semiconductor defect inspection, metrology, yield engineering, manufacturing analytics, image analysis, or a related area. Strong data analysis and programming skills, preferably with Python and SQL. Experience applying AI/ML, computer vision, statistical learning, or advanced analytics to engineering problems. Experience working with large datasets, including data extraction, manipulation, statistical analysis, visualization, and correlation. Familiarity with tools/libraries such as pandas, NumPy, scikit-learn, OpenCV, PyTorch, or TensorFlow is desirable. Strong organizational skills, attention to detail, and demonstrated analytical and problem-solving capabilities. Strong teamwork and collaboration skills, with the ability to work effectively across process, equipment, manufacturing, development, and data/IT functions. Preferred Experience with AI/ML-based wafer defect detection or classification. Experience developing automated data pipelines, dashboards, or manufacturing analytics tools. Experience with optical wafer inspection systems such as KLA Candela or Nanotronics. Knowledge of semiconductor materials, epitaxial growth, and materials characterization. Experience with DOE, SPC, process capability, and statistical modeling. Familiarity with cleanroom protocols and semiconductor wafer handling. Applicants for this position must be currently authorized to work in the United States on a full-time basis. Renesas is unable to sponsor applicants for work visas for this position Additional Information The expected annual pay range for this position is $120,000 - $160,000. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate. Renesas offers a full range of elective benefits including medical, health savings account (with applicable medical plan), dental, vision, health and/or dependent care flexible spending accounts, pre-tax commuter benefits, life insurance, AD&D, and pet insurance. In addition to elective benefit options, benefited employees receive company-paid life insurance and AD&D, LTD, short term medical benefits as well as paid sick time, paid holidays, and accrued paid vacation. New employees will attend a detailed benefit orientation to learn more about our many benefits and resources. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.