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发布于 2026-10-30 英文原文

数字设计验证工程师

Senior Staff Engineer, Design Verification (Power & Analog IC's)

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点印度 薪资面议

职位概要

瑞萨电子(Renesas)是全球领先的半导体企业,年营收超93亿美元,员工超过22,700人,业务遍及30多个国家,在汽车、工业、云和IoT领域具有重要地位。现招聘数字设计验证工程师,加入团队开发下一代电源管理解决方案。主要职责包括:定义并负责复杂SoC设计的验证计划、方法和覆盖率策略;从零搭建并实现验证环境,改进现有框架;推动模块级、子系统级和全芯片验证;构建agent、sequence、driver、monitor和scoreboard等组件;集成行业标准VIP并创建自定义transactor;主导端到端验证,包括门级仿真与调试、覆盖率分析与收敛、回归测试、故障分类及质量签核;指导初中级验证工程师;担任关键技术交付负责人。任职要求:电气工程学士或同等实践经验;12年以上UVM等验证方法学经验;熟悉行业标准仿真器、版本控制和回归系统;具备完整验证生命周期架构经验;优秀的解决问题和沟通能力;能构建scoreboard、agent、sequencer、monitor等测试平台组件;具备RTL和门级仿真调试能力,能与跨职能团队协作验证修复;能将验证测试转换为测试向量并协助ATE向量调试;了解SoC架构及混合信号设计;熟悉ADC、DAC、PLL、振荡器和PI控制器等模拟组件;掌握Perl/Python等脚本语言;熟悉定向和约束随机验证方法;精通UVM、Verilog、SystemVerilog、C/C++、Shell、Python;具备较强的调试、逻辑思维和分析能力。瑞萨提供有竞争力的薪酬福利,具体将在招聘流程中说明。

职位描述

Company Description Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3 billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies. Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications. Job Description We are looking for a motivated and talented Digital Design Verification Engineer to join our team in creating next-generation Power management solutions. Job Responsibilities Define and own verification plans, methodologies, and coverage strategies for complex SoC designs Architect and implement verification environments from scratch and enhance existing frameworks Drive block-level, subsystem-level, and full-chip verification Build Agents, sequences, drivers, monitors, and scoreboards as part of automation. Integrate industry-standard VIPs, create custom transactor. Lead end2end verification, including: Gate level simulations and debugs, coverage analysis and closure, regression, triage failures, and ensure quality sign-off Mentor junior and mid-level verification engineers Act as technical lead or owner for key verification deliverables Qualifications Bachelor's degree in Electrical Engineering or equivalent practical experience. Overall 12+ years of experience with verification methodology such as universal verification methodology (UVM). Experience with industry-standard simulators, revision control systems, and regression systems. Experience with Architecting block the full verification lifecycle. Excellent problem solving and communication skills. Construct testbenches components like scoreboard, agents, sequencers, and monitors Debugging RTL and Gate simulations and working with cross functionals team to verify fixes Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up Experience developing and maintaining verification testbenches, test cases, and test environments. Understanding of SoC architecture and functionality, Mixed signal designs. Good knowledge of analog components : ADC, DAC, PLL, Oscilators and PI controllers. Passion for learning and engineering great solutions Proven written and verbal communication skills that demonstrate clarity of thought and conviction Working knowledge of one or more scripting languages (Perl, Python) and ability to use them to automate/accelerate verification and analysis tasks Experience of directed and constrained random verification methodology Good knowledge in UVM, Verilog, SV, C/C++, Shell, Python Strong debug, logical thinking and analytical skills Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .