在招职位 0
订阅提醒 登录
发布于 2026-11-10 英文原文

首席设计验证工程师

Principal Design Verification Engineer

ルネサス エレクトロニクス

职种工程 雇用形态—
工作地点美国佐治亚州杜鲁斯(需愿意搬迁) 薪资面议

职位概要

该职位为首席设计验证工程师,负责下一代半导体存储接口产品(包括数据缓冲芯片)验证的技术领导工作。主要职责包括:主导复杂半导体设计在模块级和系统级的验证策略与执行;定义验证方法学、测试计划、覆盖率策略和验证环境;架构、开发、维护并优化SystemVerilog/UVM测试平台;推动测试开发、功能覆盖率、检查器、约束随机验证及覆盖率收敛;与RTL和设计工程师紧密合作确保设计满足功能与性能要求;分析规格、设计实现和验证结果以识别功能缺口和设计问题;推动复杂验证失败的调试与解决;开发可扩展可复用的验证组件和方法学;参与架构、可行性、设计和技术评审;为验证工程师提供技术指导和辅导。任职要求:电气工程、计算机工程、计算机科学或相关技术领域学士或硕士学位;丰富的半导体设计验证经验并具备复杂验证工作的技术主导能力;精通SystemVerilog;具有UVM大量实操经验;具备定义验证策略和制定验证计划的经验;熟悉功能验证、约束随机测试、功能覆盖率、检查器、调试和覆盖率收敛;能够独立解决复杂验证和设计问题;具备技术领导和指导能力。优先条件:具有DDR、存储接口、存储控制器、数据缓冲或相关半导体技术经验;DDR4和/或DDR5经验;复杂高速接口、协议或混合信号半导体产品验证经验;主导验证至覆盖率收敛和签核的经验。候选人须愿意搬迁至佐治亚州杜鲁斯。Renesas为嵌入式半导体解决方案提供商,全球团队超过21000名工程师,遍布30多个国家,致力于汽车、工业、基础设施和物联网领域的世界领先技术。

职位描述

Job Description *Please Note: Candidates for this role must be open to relocation to Duluth, GA. We are seeking a Principal Design Verification Engineer to provide technical leadership for verification of next-generation semiconductor memory interface products, including data buffer silicon. This role will drive verification strategy and execution for complex digital designs, working closely with design teams to ensure functionality, performance, and product requirements are met. The ideal candidate brings deep semiconductor verification expertise with SystemVerilog and UVM . Previous DDR or memory experience is an advantage, but is not required. This is an opportunity to take significant technical ownership while contributing to next-generation DDR6 technology . Key Responsibilities Lead verification strategy and execution for complex semiconductor designs at the block and system level . Define verification methodologies, test plans, coverage strategies, and verification environments. Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments . Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure. Take technical ownership of verification for assigned blocks, features, and environments from planning through signoff. Work closely with RTL and design engineers to ensure designs meet functional and performance requirements and are effectively verifiable. Analyze specifications, design implementation, and verification results to identify functional gaps and design issues. Drive debugging and resolution of complex verification failures. Develop scalable and reusable verification components, methodologies, and best practices. Identify and lead improvements in verification efficiency, quality, performance, and reuse. Participate in architecture, feasibility, design, and technical reviews. Provide technical guidance and mentorship to verification engineers. Serve as a technical expert for assigned verification methodologies and tools. Communicate verification progress, coverage, technical risks, and readiness to engineering leadership and project stakeholders. Qualifications Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field . Extensive experience in semiconductor design verification , with demonstrated technical ownership of complex verification efforts. Expert-level proficiency with SystemVerilog . Significant hands-on experience with UVM (Universal Verification Methodology) , including development and optimization of UVM-based verification environments. Experience defining verification strategies and developing verification plans from design and product specifications. Strong experience with functional verification, constrained-random testing, functional coverage, checkers, debugging, and coverage closure. Experience partnering closely with RTL/design engineering teams throughout the verification lifecycle. Demonstrated ability to independently solve complex verification and design problems. Ability to provide technical leadership and mentoring within a verification team. Preferred Qualifications Experience with DDR, memory interfaces, memory controllers, data buffers, or related semiconductor technologies . Experience with DDR4 and/or DDR5 . Verification experience with complex high-speed interfaces, protocols, or mixed-signal semiconductor products. Experience leading verification efforts through coverage closure and signoff. *Please Note: Candidates for this role must be open to relocation to Duluth, GA. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.