首席模拟设计工程师

Company Description Renesas is a global semiconductor leader shaping the backbone of next-generation automotive, industrial, cloud, and IoT innovation. With over $9.3 billion in annual revenue (2024) and a world-class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category-defining breakthroughs. The company's footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovation engine. As Japan's semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real-world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. Renesas has a growing presence in India with headcount approaching 1000+ and significant engagement with government, universities, and the semiconductor manufacturing ecosystem. With the growing importance of India as both a market and talent hub, the India for India division's mission is to create products, including power and analog ICs, mixed-signal devices, software, and system solutions, that address local market needs. This is a unique opportunity to directly influence future products for a fast-growing Indian market with distinct applications, cost structures, and localization requirements. Job Description We are seeking a Principal Analog Design Engineer with deep expertise in power management, analog, and mixed-signal IC development. This is a senior individual-contributor role requiring ownership of complex analog IP, subsystem architecture, converter design, and silicon execution from concept through production. The successful candidate will lead the design of key analog and power-management functions including switching converters, LDOs, charge pumps, references, sensors, protection circuits, data converters, and signal-conditioning blocks used across Renesas power and analog products. The role requires strong technical judgment, architecture ownership, cross-functional collaboration, and the ability to drive first-silicon success. You will be expected to operate independently, resolve ambiguous technical challenges, establish design methodology, mentor engineers, and influence product architecture and execution through deep technical expertise. Responsibilities Analog Architecture & Circuit Design Define and own the architecture of complex analog and power-management IP used in PMICs, converters, battery-management products, and mixed-signal devices. Design and own blocks such as positive and negative charge pumps, buck converters, source-sink LDOs, ultra-low-power oscillators, temperature sensors, current-sense circuits, SAR ADCs, voltage and current references, op-amps, comparators, analog buffers, level shifters, and protection circuits. Translate product and top-level chip requirements into detailed block specifications, architecture decisions, circuit implementations, and verification plans. Perform block-level error budgeting and system-level trade-off analysis across performance, area, power, cost, robustness, and manufacturability. Converter & Control Loop Design Independently architect and design complete switching converters including buck, boost, and buck-boost converters, as well as LDOs and point-of-load devices. Demonstrate deep understanding of analog feedback loops, control-loop stability, compensation implementation, and trade-offs across compensation strategies. Evaluate control architectures such as constant-frequency, constant-on-time, constant-off-time, voltage-mode, and current-mode control, and select the appropriate approach for product requirements. Ensure robust converter performance across process, voltage, temperature, load, line, startup, shutdown, and fault conditions. Verification, Silicon & Production Support Drive analog verification and simulation strategy across schematic, extracted, pre-layout, and post-layout environments. Optimize simulation setups based on speed, convergence, accuracy, and parasitic conditions, and resolve simulator, model, and tool-related challenges. Own or support silicon validation, characterization, debug, qualification, production readiness, and root-cause analysis for silicon issues. Collaborate with product engineering, test engineering, applications, reliability, and manufacturing teams across the complete product lifecycle. Physical Design, Reliability & Sign-off Collaborate closely with layout engineers from floor planning through chip-top completion, extraction, verification, and tape-out. Guide layout trade-offs related to matching, noise, parasitics, isolation, current density, electromigration, IR drop, thermal behavior, and high-current operation. Demonstrate strong understanding of ESD, latch-up, I/O-ring protection, and other IC-level reliability requirements. Review physical implementation and extracted performance to ensure the design meets electrical, yield, reliability, and manufacturability targets. Technical Leadership & Methodology Drive analog design methodology, checklists, design reviews, reusable IP practices, and quality standards from concept through silicon success. Lead technical reviews and provide clear architecture, design, verification, risk, and sign-off assessments to project leadership. Mentor junior and mid-level engineers through architecture reviews, circuit design, simulation strategy, layout collaboration, and silicon debug. Influence product architecture and technical roadmap decisions through demonstrated technical depth, while operating as a senior individual contributor rather than a formal people manager. Qualifications Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline. 15+ years of relevant experience in analog, mixed-signal, or power-management IC design. Demonstrated ownership of complex analog IP, converter subsystems, or complete smaller ICs from architecture through silicon and production. Deep hands-on expertise in PMICs, switching regulators, LDOs, charge pumps, and complex analog IP development. Strong understanding of analog feedback loops, control-loop compensation, stability analysis, and converter-architecture trade-offs. Experience with references, op-amps, comparators, buffers, level shifters, oscillators, sensors, current sensing, ADCs, and protection circuitry. Experience with industry-standard schematic design, simulation, extraction, and post-layout verification flows and tools. Strong understanding of analog layout effects, parasitics, matching, noise, reliability, ESD, latch-up, and IC-level robustness. Experience taking products through design, verification, tape-out, silicon validation, debug, qualification support, and production release. Proven ability to establish design methodology, lead technical reviews, mentor engineers, and influence cross-functional decisions without requiring formal people-management authority. Strong communication and collaboration skills across global, multisite, and multicultural teams. Self-driven, results-oriented, and able to deliver high-quality designs under tight schedules with limited supervision. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring pro